In clock/data recovery and various phase/timing control operations, phase or timing adjustments are often performed after a phase or timing error is detected. A phase detector or comparator is necessary for both traditional, analog-based Phase Locked Loop (PLL) and for digital, delay line based systems. Even in analog based PLL systems, it is known for the phase detector to use digital circuits, such as the balanced modulator circuit using exclusive-OR gates and the sequential phase detector or so-called "9 gate phase detector" using a number of cross-coupled RS flip-flops. However, the output from those types of phase detector circuits can not be directly used by the subsequent circuitry which receives the output signal representative of phase error. This is because the magnitude of the phase error is represented either in the form of pulse width of the output signal, such as the case of the balanced modulator, or in a form of the pulse width difference between two output signals, such as the case of the sequential phase detector. In analog based phase detector systems, the function of the phase detector is to provide an output voltage proportional to the phase difference of two periodic input signals at the same frequency. Conversion of pulse width to voltage is then necessary. The digital output signal from the phase detector is converted into an analog voltage by using, for example, a so called charge pump and a low pass filter. This analogue voltage error signal is then used to control a Voltage Controlled Oscillator (VCO), which changes the oscillator frequency to slowly achieve the phase adjustment or alignment over a number of cycles, since the amount of the necessary phase change is the integral of the difference between the VCO frequency and the reference frequency.